In an error data correcting system of this type, which has been proposed heretofore in this field, n data words W1 to Wn each containing m/n bits and additionally include a first check code ##EQU1## as the sum of bits corresponding to the data words and a second check code ##EQU2## as the sum of the bits corresponding to the signals generated through the operation of a polynomial X.sup.m +X.sup.g +1 by an auxiliary matrix (T). The error data correcting system can correct up to two error words in the N data words by using an M matrix generator for decoding.
A ROM (read only memory) has generally been used from the M matrix generator for decoding, because of the time restriction in the decoding process.
In the case of an audio PCM recorder such as a record/reproduction system, one word commonly includes 12 to 16 bits. If the error data correcting system is applied to such a system, the memory capacity of the ROM that is used must be very large and an address counter capable of formulating the large address fields for the ROM is needed. The circuit construction for such an overall system is complicated. Additionally, very large number of components is necessary when the circuit is fabricated by LSI technology.